1. Field of the Invention
The present invention relates to a semiconductor device having a solid state image sensing device and a manufacturing method thereof.
2. Description of the Background Art
In recent years, a solid state image sensing device using an amplification-type sensor has been proposed as one type of solid state image sensing devices. This device features that a light signal detected by a photoelectric transfer storage section is amplified in the proximity of the photoelectric transfer storage section.
FIG. 22 is a drawing that shows a circuit construction of a CMOS-type (Complementary Metal Oxide Semiconductor) image sensor serving as a solid state image sensing device. As illustrated in FIG. 22, unit pixels or unit cells C are arranged in a matrix format, and each of the cells C is connected to a vertical shift register and a horizontal shift register.
Each of the unit cells C has a photodiode PD, a transfer switch M1, a reset switch M2, an amplifier M3 and a selection switch M4. The photodiode PD transfers incident light to an electric signal. The transfer switch M1, which is controlled by a signal sent from the vertical shift register, transfers the electric signal thus transferred to the amplifier M3. The reset switch M2 resets a signal charge, and the amplifier M3 amplifies the electric signal.
Here, the transfer switch M1, the reset switch M2, the amplifier M3 and the selection switch M4 are respectively constituted by MOS transistors.
For example, U.S. Pat. No. 5,898,196 discloses a specific construction of such a solid state image sensing device.
FIG. 23 is a schematic cross-sectional view that shows the construction of a semiconductor device having the solid state image sensing device disclosed in U.S. Pat. No. 5,898,196. As illustrated in FIG. 23, a photodiode PD and a transfer switch M1 constituting the solid state image sensing device are shown in a pixel region, and a transistor Tn, etc. constituting peripheral circuits such as vertical and horizontal shift registers are shown in a logic region.
A pxe2x88x92 impurity region 102 and p+ impurity region 102a are formed on a p+ region 101, and both of the solid state image sensing device and the peripheral circuit device are formed in the pxe2x88x92 impurity region 102.
The photodiode PD in the pixel region is constituted by the pxe2x88x92 impurity region 102 and an nxe2x88x92 impurity region 104. A p+ impurity region 105 is formed on the upper portion of the nxe2x88x92 impurity region 104.
The transfer switch M1 is provided with an nxe2x88x92 source region 104, an n+ drain (FD) region 106 and a gate electrode layer 108. The nxe2x88x92 source region 104 and the n+ drain region 106 are formed with a predetermined distance. The gate electrode layer 108 is formed on an region sandwiched by the nxe2x88x92 source region 104 and the n+ drain region 106 through a gate insulation layer 107. Here, the nxe2x88x92 impurity region 104 of the photodiode PD and the nxe2x88x92 source region 104 of the transfer switch M1 are constituted by the same impurity region.
The MOS transistor Tn in the logic region is provided with a pair of n+ source/drain regions 122 and a gate electrode layer 124. The pair of n+ source/drain regions are formed with a predetermined distance in between. The gate electrode layer 124 is formed on an region sandwiched by the pair of n+ source/drain regions through a gate insulation layer 123.
The pixel region and the logic region are electrically separated by a separation region 103 formed on the surface of the semiconductor substrate 101.
In the above-mentioned construction of FIG. 23, the pxe2x88x92 impurity region 102 in which the pixel cell is formed and the pxe2x88x92 impurity region 102 in which the peripheral circuit element is formed are integrally formed. This construction has raised a problem of degradation in the pixel characteristic (SIN ratio) of the pixel cell. A detailed explanation will be given of this problem.
As illustrated in FIG. 23, in the MOS transistor Tn of the logic region, when the gate length (that is, the channel length) is shortened with the voltage between the drain and source being constant, the electric field inside a void layer located at a drain end portion of a channel becomes extremely great. As a result, an avalanche phenomenon in which electrons are accelerated to high speeds, and collide with atoms to generate electrons and positive holes in a manner like an avalanche takes place. One portion of a charge such as a hot carrier caused by this phenomenon is dispersed inside the pxe2x88x92 impurity region 102. At this time, in the case when the pxe2x88x92 impurity regions 102 of the pixel region and the logic region are integrally formed, the charge such as a hot carrier easily invade the pixel region. As a result, the charge such as a hot carrier forms a noise component, thereby causing degradation in the pixel characteristic (SIN ratio).
Here, supposing that the generation of charge in the photodiode PD portion is QP and the capacity in the FD portion is CFD, the output voltage Vout is represented by Vout=QP/CFD.
When the above-mentioned noise component Q1 exists, the corresponding error xcex94Vout=Q1/FFD is generated. Consequently, in the case of no light irradiation, Vout (noise) is increased by the value corresponding to xcex94Vout, with the result that the sensitivity as the solid state image sensing device, that is, the S/N ratio, is lowered.
Moreover, at the time when the substrate is transported or when the substrate is wet-etched, transition metals, such as Cr, Fe, Ni, Co, etc., or heavy metals such as Cu, Au, etc., tend to adhere to the vicinity of the surface of the substrate, or minute defects such as deposition of oxides tend to be produced. In this case, these transition metals, heavy metals, minute defects, etc. easily invade from the logic region to the pixel region, causing a leak current and resulting in degradation in the pixel characteristic (S/N ratio).
The present invention has been devised to solve the above-mentioned problems, and its objective is to provide a semiconductor device having a solid state image sensing device and a manufacturing method thereof, which can improve the pixel characteristic by preventing a hot carrier, transition metals, etc. from invading from a peripheral circuit region to a pixel region.
The semiconductor device having a solid state image sensing device of the present invention is provided with a semiconductor substrate, first and second well regions, a plurality of unit cells and a peripheral circuit element. The semiconductor substrate is a first conductive type, and has a main surface. The first and second well regions are a second conductive type, and formed on the main surface of the semiconductor substrate. Each of the unit cells is formed on the first well region, and is provided with a photoelectric transfer element for transferring light to an electric signal. The peripheral circuit element, which is formed on the second well region, is used for controlling the unit cells. The first well region is surrounded by a region of the first conductive type on the periphery thereof so as to be separated from the second well region.
In accordance with the semiconductor device having a solid state image sensing device of the present invention, the first well region in which a plurality of unit cells are formed and the second well region in which a peripheral circuit element is formed are separated from each other; therefore, it is possible to limit a hot carrier caused in the peripheral circuit element from invading the first well region. Moreover, it is also possible to limit transition metals, heavy metals and minute defects in the second well region from invading the first well region. For this reason, it is possible to reduce noise components from the photoelectric transfer element as compared with conventional devices, and consequently to improve the pixel characteristic (S/N ratio).
In the above-mentioned semiconductor device having a solid state image sensing device, it is preferable to form a gettering layer below the first well region.
With this arrangement, transition metals, heavy metals and minute defects in the first well region and transition metals, heavy metals and minute defects dispersed toward the first well region side are taken into the gettering layer so that it is possible to further improve the pixel characteristic (S/N ratio).
In the above-mentioned semiconductor device having a solid state image sensing device, it is preferable to provide the gettering layer of the first conductive type, which has an impurity concentration higher than the impurity concentration of the semiconductor substrate.
The presence of the high-concentration gettering layer makes it possible to reduce the resistance of the substrate portion, and consequently to reduce the occurrence of latch-up that tends to raise problems in the CMOS construction. Moreover, it is possible to limit a charge such as a hot carrier generated in the peripheral circuit element from dispersing to the first well region side, and consequently to further improve the pixel characteristic (S/N ratio).
In the above-mentioned semiconductor device having a solid state image sensing device, it is preferable to provide the gettering layer of the second conductive type, which has an impurity concentration higher than the impurity concentration of the first well region.
The presence of the high-concentration gettering layer makes it possible to reduce the resistance of the substrate portion, and consequently to reduce the occurrence of latch-up that tends to raise problems in the CMOS construction. Moreover, it is possible to limit a charge such as a hot carrier generated in the peripheral circuit element from dispersing to the first well region side, and consequently to further improve the pixel characteristic (S/N ratio).
In the above-mentioned semiconductor device having a solid state image sensing device, it is preferable to provide a first separating impurity region of the first conductive type, which surrounds a side portion of the first well region, and has an impurity concentration higher than the impurity concentration of the semiconductor substrate.
This arrangement forms the first separating impurity region having a high concentration interpolated between the first well region and the second well region. For this reason, it is possible to prevent a charge such as a hot carrier, transition metals, etc. within the second well region from invading the first well region more effectively. Therefore, it is possible to reduce the leak current, to prevent reduction in the sensitivity, and to improve resistance to latch-up.
In the above-mentioned semiconductor device having a solid state image sensing device, it is preferable to further provide a second separating impurity region of the first conductive type, which is formed below the first well region, and has an impurity concentration higher than the impurity concentration of the semiconductor substrate.
The presence of this high-concentration second separating impurity region makes it possible to reduce the resistance of the substrate portion, and consequently to reduce the occurrence of latch-up that tends to raise problems in the CMOS construction. Moreover, it is possible to limit a charge such as a hot carrier generated in the peripheral circuit element from dispersing to the first well region side, and consequently to further improve the pixel characteristic (S/N ratio).
The manufacturing method of a semiconductor device having a solid state image sensing device of the present invention is provided with the following processes.
First, an impurity of the second conductive type is injected to the main surface of a semiconductor substrate of the first conductive type so that the first and second well regions of the second conductive type that are separated from each other are formed. Then, a plurality of unit cells each of which has a photoelectric transfer element for transferring light to an electric signal are formed in the first well region. Further, a peripheral circuit element for controlling the unit cells is formed in the second well region.
In the manufacturing method of the semiconductor device having a solid state image sensing device of the present invention, the first well region in which the unit cells are formed and the second well region in which the peripheral circuit element is formed are formed in a separate manner from each other; thus, it is possible to limit a hot carrier generated in the peripheral circuit element from invading the first well region. Moreover, it is also possible to limit transition metals, heavy metals and minute defects in the second well region from invading the first well region. For this reason, it is possible to reduce noise components from the photoelectric transfer element as compared with conventional devices, and consequently to improve the pixel characteristic (S/N ratio).
In the above-mentioned manufacturing method of a semiconductor device having a solid state image sensing device, it is preferable to further provide a process for forming a gettering layer below the first well region.
With this arrangement, transition metals, heavy metals and minute defects in the first well region and transition metals, heavy metals and minute defects dispersed toward the first well region side are taken into the gettering layer so that it is possible to further improve the pixel characteristic (S/N ratio).
In the above-mentioned manufacturing method of a semiconductor device having a solid state image sensing device, the gettering layer is preferably formed by exposing a semiconductor substrate to a heated gas so as to inject an impurity into the semiconductor substrate.
This makes it possible to easily form the gettering layer.
In the above-mentioned manufacturing method of a semiconductor device having a solid state image sensing device, the gettering layer is preferably formed by ion-injecting an impurity to a semiconductor substrate prior to forming the first and second well regions.
By using the ion-injecting method, it is possible to easily form the gettering layer with a high controlling property.
In the above-mentioned manufacturing method of a semiconductor device having a solid state image sensing device, the gettering layer is preferably formed by ion-injecting an impurity to a semiconductor substrate after forming the first and second well regions.
In this manner, by using the ion-injecting method, it is possible to form the gettering layer after forming the first and second well regions.
In the above-mentioned manufacturing method of a semiconductor device having a solid state image sensing device, it is preferable to further provide a process for forming a separating impurity region of the first conductive type, which surrounds a side portion of the first well region, and has an impurity concentration higher than the impurity concentration of the semiconductor substrate.
This process provides the separating impurity region having a high concentration interpolated between the first well region and the second well region. For this reason, it is possible to prevent a charge such as a hot carrier, transition metals, etc. within the second well region from invading the first well region more effectively. Therefore, it is possible to reduce the leak current, to prevent reduction in the sensitivity, and to improve resistance to latch-up.
In the above-mentioned manufacturing method of a semiconductor device having a solid state image sensing device, the separating impurity region is preferably formed by exposing a semiconductor substrate to a heated gas so as to inject an impurity into the semiconductor substrate.
This makes it possible to easily form the separating impurity region.
In the above-mentioned manufacturing method of a semiconductor device having a solid state image sensing device, the separating impurity region is preferably formed by ion-injecting an impurity to a semiconductor substrate.
By using the ion-injecting method, it is possible to easily form the separating impurity region with a high controlling property.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.